The present invention relates, in general, to electronics and, more particularly, to methods of forming semiconductors and structures therefore.
Metal-oxide semiconductor field effect transistors (MOSFETs) are a common type of power switching device. A MOSFET device includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate structure provided adjacent to the channel region. The gate structure includes a conductive gate electrode layer disposed adjacent to and separated from the channel region by a thin dielectric layer.
When a MOSFET device is in the on state, a voltage is applied to the gate structure to form a conduction channel region between the source and drain regions, which allows current to flow through the device. In the off state, any voltage applied to the gate structure is sufficiently low so that a conduction channel does not form, and thus current flow does not occur. During the off state, the device must support a high voltage between the source region and the drain region.
Today's higher voltage power switch market is driven by at least two major parameters, which include breakdown voltage (BVdss) and on-state resistance (Rdson). For a specific application, a minimum breakdown voltage is required, and in practice, designers typically can meet a BVdss specification. However, this is often at the expense of Rdson. This trade-off in performance is a major design challenge for manufacturers and users of high voltage power switching devices.
Recently, superjunction devices have gained in popularity to improve the trade-off between Rdson and BVdss. In previous n-channel superjunction devices, multiple heavily-doped diffused n-type and p-type regions replace one lightly doped n-type epitaxial region. In the on state, current flows through the heavily doped n-type regions, which lowers Rdson. In the off or blocking state, the heavily doped n-type and p-type regions deplete into or compensate each other to provide a high BVdss. Although superjunction devices look promising, significant challenges still exist in manufacturing them.
Another problem with previous superjunction devices is that the energy capability (Eas) under unclamped inductive switching (UIS) testing is often too low under optimum charge balance (for example, CB approaching 0%) or within a desired charge balance window. Such inadequate Eas capability is believed to be from low snapback current (Isnapback) in the reverse blocking IdVd curve. A low Isnapback can produce a pure electrical failure observed at few nanoseconds after switching-off the device in the typical UIS test. The electrical failure can occur when a negative differential resistance is reached at a certain region of the active area, thus producing a non-uniform current distribution and, eventually, a current focalization or a “hot spot”. Additionally, a low Isnapback can limit the energy capability under other tests, such as reverse recovery tests.
Accordingly, it is desirable to have a structure for and method of making a charge balanced semiconductor device that improves Eas performance for an optimum charge balance and/or a selected charge balance window. It would be beneficial if the structure and method maintained the design trade-offs between Eas, Rdson, and BVdss. Additionally, it would beneficial if the structure and method did not add significant process complexity or excessive costs.
For simplicity and clarity of the illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. For clarity of the drawings, certain regions of device structures, such as doped regions or dielectric regions, may be illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that, due to the diffusion and activation of dopants or formation of layers, the edges of such regions generally may not be straight lines and that the corners may not be precise angles. Furthermore, the term “major surface” when used in conjunction with a semiconductor region, wafer, or substrate means the surface of the semiconductor region, wafer, or substrate that forms an interface with another material, such as a dielectric, an insulator, a conductor, or a polycrystalline semiconductor. The major surface can have a topography that changes in the x, y and z directions.